Efficient FPGA Implementation Architecture of Fast FIR Algorithm Using Han-Carlson Adder Based Vedic Multiplier

Abstract

Parallel FIR filter is the need of many low power and high speed DSP applications. In this paper, fast FIR algorithm based parallel symmetric FIR filter using Han-Carlson adder based vedic multiplier is proposed. FFA algorithm reduces the multiplier count as compared to the traditional parallel design. In order to improve the performance of the proposed filter, recently developed Han-Carlson adder based Vedic multiplier is used. In the proposed design the adder unit is also implemented using Han-Carlson adder. In the proposed design two and three parallel FIR filters of order 24 and 72 are implemented using VHDL. The implementation results show that the proposed architecture provides low critical path delay and power dissipation as compared to the conventional one. With the advantage of low delay and power, proposed architecture is useful in modern signal processing and communication applications.