VHDL Fault Simulation and Automatic Test Pattern Generation Requirements Document.

Abstract

Abstract : This document describes the requirements for a design automation tool that performs fault simulation and fault grading using the Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL). The goal is to develop a tool which can automatically perform fault grading using fault simulation on any VHDL model using any fully compliant VHDL simulator. The current state of the art for VHDL-based fault simulation is very limited. Preliminary research has been performed for fault insertion techniques, but tools do not exist which perform VHDL fault simulation/fault grading. Reference 2, developed to assist in the preparation of this requirements document summarizes the following items: (1) fault simulation techniques described in the literature, (2) VHDL-based fault simulation techniques, (3) commercial fault simulation products which accept VHDL models as input and perform fault simulation without a VHDL simulator, (4) fault grading techniques, and (5) test pattern generation methods. The term VHDL-based fault simulation is defined in this document as a fault simulation technique which uses a fully compliant VHDL simulator to perform fault simulation. There exist numerous commercial products which accept VHDL models as input and perform fault simulation. However, these products perform fault simulation using a proprietary (nonVHDL) simulation engine. This type of commercial fault simulation tool is a nonVHDL-based fault simulation technique. The extensive review of the state of the art has revealed that VHDL-based fault simulation tools do not exist.