Analysis of the gap between behavioral and gate level fault simulation

Abstract

A VHSIC Hardware Description Language (VHDL) Automatic Test Pattern Generator (ATPG) system to perform behavioral fault modeling and simulation is discussed. The input to the VHDL ATPG system is VHDL at the behavioral level. The behavioral fault model analyzer generates the behavioral faulty files for each fault simulated. The behavioral faulty files are input to both the behavioral fault simulator and the test bench generator. The test bench generator, at the request of user, produces a fault simulation test bench which is applied to the behavioral fault simulator for simulating the faulty files and reference model, respectively. The outputs of these two simulators are compared in the fault simulation comparator which generates the simulation report. The authors analyze the gap of the fault model and fault simulation between the behavioral level and gate level circuit description and show the one to one correspondence with typical examples. The authors demonstrate the effectiveness of behavioral fault modeling and simulation by illustrations of applying the method to practical examples. >