Behavioral test generation/fault simulation

Abstract

A complete behavioral fault simulation and automatic test pattern generation (ATPG) system for circuits modeled in VHDL has been presented in this research. Ten different behavioral fault models were selected and used to generate test patterns through fault simulation. One major advantage of the current system is that full VHDL (IEEE-STD 1076) constructs can be handled because fault simulation are performed by comparing the simulation results of good and faulty models utilizing a VHDL simulator. Areas of future research include the refinement of existing fault models, defining new behavioral fault models to reduce the gap between the behavioral fault models and gate-level failures, and the development of a better test pattern generator for target faults. Another valuable enhancement would be to run fault simulation in parallel, by embedding multiple faulty models into one test bench to simulate many faults concurrently. This would speed up the behavioral fault simulation in an efficient way. Gate-level fault simulation is not an effective solution for complex microcircuits. The results of this research show that behavioral fault simulation will remain as a highly attractive alternative for the future generation of VLSI and system-on-chips (SoC).