Behavioral fault modeling and simulation of phase-locked loops using a VHDL-A like language

Abstract

A new methodology called induced behavioral fault modeling is presented for fault simulation and testing of analog and mixed-signal circuits, and demonstrated using voltage controlled oscillators and phase-locked loops. The key of this methodology is to use actual layout and process defect information to derive a set of realistic faults at the transistor level, and to generate a small set of behavioral fault models-in a mixed-signal hardware description language-that abstracts the derived transistor-level faults. While ensuring the same fault coverage as transistor-level fault modeling, induced behavioral fault modeling offers significant advantage in simulation efficiency and modeling capacity.