Verification of Synchronous Elastic Processors

Abstract

We develop a formal verification procedure to check the correctness of synchronous elastic pipelined processors against their synchronous parent systems. Note that the goal of the verification procedure is not to establish the correctness of the algorithm for synthesizing elastic circuits, but instead, to find bugs and formally prove the correctness of elasticized designs. Dataflow through elastic architectures is complicated by the insertion of any number of elastic buffers in any place in the design. We introduce elastic token-flow diagrams, which are used to track the flow of data in elastic architectures. We provide a method to construct such diagrams. We also develop a highly automated and systematic procedure based on elastic token-flow diagrams that computes functions that map states of elastic systems to states of the synchronous parent systems. Such functions, known as refinement maps are used to compare behaviors of elastic and synchronous systems and hence prove their equivalence. We elasticized a five-stage DLX processor that enables the insertion of buffers in its data path. We constructed several elastic processors by introducing up to five elastic buffers at various places in the data path and verified equivalence with their synchronous parent processor.