Abstract
This chapter discusses the effects of pipelining on the performance of high speed synchronous digital systems. In particular, the tradeoff between clock frequency and latency is described in terms of the circuit characteristics of a pipelined data path [1,2]. The design of the clock distribution network synchronizing the signal flow between each data path can significantly affect system performance. Timing characteristics of the clock distribution network are described in terms of how system performance can be either enhanced or degraded. A design paradigm relating latency and clock frequency as a function of the level of pipelining is developed for studying the performance of a synchronous system. This perspective permits the development of design equations for constrained and unconstrained design problems which describe these performance parameters in terms of the delays of the logic, interconnect, and registers, the nature of the clock distribution network, and the number of logic stages.
Published Version
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