Verification and reduction of surface charging during high/medium current implantations by implementing plasma damage monitoring

Abstract

Dielectric charging damage during IC processing is the result of complex interactions between the wafer environment and the wafer itself. Understanding these interactions and recognizing the relative importance of the different mechanisms capable of causing damage, is essential for successful diagnosis and control of charging damage during wafer manufacturing. Avoiding gate oxide damage due to excessive wafer charging has always been an issue with high current implanters. Whether it is caused by shrinking of device dimensions, or its use as a backup for high current applications, charging level awareness becomes the primary limiting factor for running higher beam currents in medium current implanters. Flooding the wafer with low energy electrons from a plasma flood gun (PFG) which is a self-regulated electron shower, has been the widely accepted means of reducing wafer charging. The effectiveness of the PFG in reducing charging as a function of primary ion current, voltage of electron extraction from the PFG, ion beam positioning and other parameters in a beam path to the wafer have been investigated. This investigation was carried out on medium and high current implanters, VIISta 810HP and VIIStaHC respectively, using the plasma damage monitoring (PDM) technique on metrology tool FAaST350.