Variation-aware approaches with power improvement in digital circuits

Abstract

In submicron technology, during the fabrication process factors like lithography and lens defect can change some of the physical parameters of transistors and interconnects. This change can modify the transistor electrical characteristics such as current, threshold voltage and gate capacitance, and thus it causes variation in power, delay and performance of the circuit. Process variation has become one of designer׳s challenges to the point that in below 45nm technology it is considered as the most important issue in reliability. Power consumption and transistors variation are limiting factors to physical scalability. In this paper, we propose two approaches to reduce D2D and WID variations effects on digital CMOS circuits, at design time. The first approach concerns a variation-aware algorithm capable of extracting optimal design parameters to decrease variation and power. The second approach, using transistor stacking will help further reduce variation and power. Applying the algorithm on a digital design and according to parameters behavior in the presence of variation, we extract for each parameter value that will lead to power and variation reduction. On the other hand, with the stacking approach only basic gates are considered and subsequently gate configurations that reduce power and variation are proposed. The proposed approaches could be used identically for synchronous and asynchronous circuits. To prove this claim, we apply our approaches to a network-on-chip asynchronous router and a circuit from the ISCAS85 benchmark. All simulations are done in 32nm technology using the HSPICE tool. The proposed algorithm similar to Monte Carlo simulation achieves the same results; however with lower execution time. The application of stacking approach to both asynchronous router and ISCAS85 circuit reduces variation effects up to 40.9% and 13.35%, respectively.