Variable-shaped EB sub-half-micron lithography applied to high-power GaAs FET’s

Abstract

This paper is the first on applying a variable‐shaped electron‐beam (EB) lithography process to microwave high‐power GaAs FET’s with sub‐half‐micron (0.3–0.4 μm) gate length. By developing a new lift‐off process using a trilevel resist structure, the gates with interdigital structure are offset toward source electrodes in deeply recessed channels (0.35 μm depth) in order to reduce source parasitic resistance and improve drain breakdown voltage. An 80% chip yield was obtained for the FET with 0.4 μm gate length (Lg) and 6 mm total gate width (ZT). For the FET with 0.6 μm offset gate and ZT=1.5 mm, 1.0 W output power with 5 dB associated gain (Ga), 8.5 dB linear gain (GL), and 27.4% power added efficiency were obtained at 10 GHz. The present device, which had the 1.6 dB back off at the −30 dB third‐order intermodulation distortion (IM3) point, can also lead to significantly low distortion in linearity at microwave frequencies.