Use of the Modification of the Petri Nets Algorithm for the Logic Simulation of Gate-Level Logic Circuits

Abstract

An event-driven simulation algorithm is the main algorithm for the simulation of digital circuits used in digital simulators. However, the implicit choice of the firing sequence of simultaneously switching signals can lead to differences in the simulation results. A new algorithm for the event-driven logic simulation of digital integrated circuits based on the use of the modified mathematical apparatus of Petri nets is proposed. The Petri nets apparatus makes it possible to simulate parallel constructs using sequential instructions. Therefore, there is no need to separate events with a δ-delay. The described approach makes it possible to eliminate the ambiguity of switching signals that occur at the same time due to not using the δ-delay. The results of the algorithm’s work are presented using the gate-level simulation of a number of combinational and sequential circuits as an example. The obtained timing diagrams, as well as the simulation time, show that the proposed algorithm is not inferior to the existing simulation tools in terms of reliability and performance.