Use of a CPLD in an Introductory Logic Circuits Course with Software and Hardware Upgrade

Abstract

This paper documents our continued efforts to integrate the Complex Programmable Logic Device (CPLD) into our introductory logic circuits course at the University of Hartford. Although programmable logic devices (PLDs) have long been introduced in our advanced courses, the widespread acceptance demands that PLDs be introduced earlier in the electrical and computer engineering curriculum. In the fall semester of 2011 we selected a CPLD for the introductory logic circuits course because it allows for an experience that includes modern design tools and hands-on activities with the aid of a CPLD module. In prior research we found that in using the CPLD module, students can easily identify the CPLD and with modest wiring they can construct circuits that they feel are both satisfying and engaging. In this paper, our most recent developments, which include both software and hardware upgrades, along with student feedback are documented. With the Xilinx XC9536 CPLDs now obsolete we faced the inevitable trend to lower Voltage logic and adopted a newer CPLD. The newer XC9500XL series CPLDs require 3.3V power which is not compatible with any commercially available trainer that we are aware of, so we designed our own 3.3 Volt logic trainer. The CPLD module and trainer artwork are available at our webpage under free software license for your use. On the software front, we revised our tutorial and started having our students work with test bench files. The CAD software used in our labs was upgraded from Xilinx ISE Version 10.1 to Version 13.2. In the past, we specifically chose Xilinx ISE 10.1 32-bit version for its graphical test bench generator which is very convenient for students to use when performing simulation. Unfortunately, this feature is absent in the ISE 10.1 64-bit version and subsequent versions. On the other hand, version 13.2 is more stable than version 10.1. In adopting version 13.2, we had concerns regarding how students would generate the simulation test bench, which involves modifying VHDL codes, since students do not learn to write hardware description language (HDL) in our introductory logic circuits course. Xilinx ISE provides an aid by generating a skeleton which our students are able to modify for their own use following the instructions in our revised tutorial. New lecture material was developed to help students understand these upgrades. Based on student feedback we also provided some historical context with regard to the current state of the art in logic circuits. New lab content was developed to address some concerns from our previous experience which include: a) start-up activities to help students master the CAD software better and earlier in the course; b) incorporating the use of hierarchical design earlier and in more experiments. We present our students’ feedback along with the instructors’ observations concerning both the hardware and software upgrades and other changes that were made. In closing, we present our future plans.