Accelerated life testing of Field Programmable Gate Arrays

Abstract

Advent of VLSI technology has paved the way for Programmable Logic Devices (PLD), which are widely used as the basic building blocks in high integrity electronic systems. PLDs are considered for their robust features such as high gate density, performance, speed etc. For PFBR Instrumentation and Control systems, PLDs are extensively used to implement digital designs such as VME bus interface logic, control logic and sequencing logic etc. Types of PLDs, such as Field Programmable Gate Arrays, Complex Programmable Logic Devices and Gate Array Logic devices are used in Core Temperature Monitoring System and Safety logics of shutdown systems. Since these devices are reliable as per the manufacturer's specification, they were used in R & D facilities like Fast Breeder Test Reactor and Augmented Boron Enrichment Plant as test beds. However, in order to use PLDs in commercial Nuclear Power Plant (in PFBR), it is vital to know about their performance in other critical applications. The availability of required data is limited, other than for space applications. So, it is proposed to conduct Quantitative Accelerated Life Tests (QALT) for the PLDs. QALT is designed to produce the data required for accelerated life data analysis. This analysis method uses life data obtained under accelerated conditions to extrapolate an estimated probability density function for the product under normal use conditions. Accelerated life tests are conducted on products to understand their failure modes and life characteristics. The products are subjected to enhanced stresses in order to force the products to fail early than they would normally, under use conditions. This process reduces test time. This paper discusses the methodology adapted to perform the Accelerated Life Test for the above mentioned PLDs.