Compact CPLD Board Designing and Implemented for Digital Clock

Abstract

ABSTRACT The work describes the design and implementation of Complex Programmable Logic Devices (CPLDs) board for many digital applications in the educational and research field laboratory in the university. The objective of designed board is to implement the digital logic, which can be used for any digital application and take advantages of CPLDs features like reconfigurable architecture, high speed operation, pin locking, in-system programming (ISP) for digital system design. This CPLD board size is relatively compact; so it can be easily mounted. On board power supply and variable frequency oscillator improves functionality of overall board. The design includes some cost effective embedded control and communication interface to build digital application to work more efficiently in the market. Keywords Reconfigurable architecture, CPLD, Digital Design, Digital Clock, PLDs. 1. NTRODUCTION The process of designing digital hardware has changed dramatically over the past few years. Unlike previous generations of technology, in which board-level prototype designs included large numbers of SSI chips containing basic gates, virtually every prototype digital design produced today consists mostly of programmable logic devices [7]. This applies not only to digital logic circuits, but also for robotics applications like sensing, actuation, manipulation. Programmable logic offers the digital circuit designer the possibility of changing design function even after it has been built. A programmable logic device (PLD) can be programmed, erased, and reprogrammed many times, allowing easier prototyping and design modification. PLDs can be programmed from personal computer (PC) or workstation running special software. This software is often associated with a set of programs that allow us to design circuits for various PLDs [2]. For successful implementation of digital design and, it is essential to have suitable CPLD board for teaching and learning CPLD programming as well as for real time application development. It should be affordable, user friendly and flexible. The following sections describe the design of the CPLD board, application of the board, the benefits of the board, and finally concluding remarks. The implementation of the CPLD board used here is digital clock. The complete module consists of many sub modules of onboard and in CPLD chip like power supply, variable frequency crystal oscillator and I/Os are onboard and counter, multiplex, decoder, and comparator are designed inside the CPLD chip. The time displayed is in the form of binary coded decimal and seven segments.