UNIFIED TECHNIQUE FOR ON-LINE TESTING OF DIGITAL CIRCUITS: DELAY AND STUCK-AT FAULT MODELS

Abstract

This work is concerned with the development of generic, nonintrusive, and flexible algorithms for the design of digital circuits with on-line testing (OLT) capability. Most of the works presented in the literature on OLT have used single stuck at (s - a) fault models. However, in the deep submicron technology, single s - a fault models may not capture more than a fraction of the real defects. To cater to the problem it is now advocated that additional fault models such as bridging faults, transition faults, delay faults, etc., are also used. The proposed technique is one of the first works that facilitates a unified scheme for on-line detection of delay faults and s - a faults with a high value of n for n-Detect tests. The technique can handle generic digital circuits with cell count as high as 15,000 and having the order of 2500 states. Results for the design of on-line detectors for various ISCAS89 benchmark circuits are provided. The results illustrate that with marginal increase in the area overhead, if compared to the ones with single s - a fault coverage only, the proposed scheme also provides coverage for the delay faults.