Concurrent Testing of Digital Circuits for Advanced Fault Models

Abstract

This work is concerned with the development of generic, non-intrusive and flexible algorithms for the design of digital circuits with on line testing (OLT) capability. Most of the works presented in the literature on OLT have used single stuck at fault models. However, in deep sub micron era single s-a fault models may not capture more than a fraction of the real defects. To cater to the problem it is now advocated that additional fault models such as resistive bridging faults, transition faults, delay faults etc. are also used. The proposed technique is one of the first works that enables on-line detection of resistive bridging faults and provides a high value of n for the n-detect tests. The technique can handle generic digital circuits with cell count as high as 15,000 and having the order of 2500 states. Results for design of on-line detectors for various ISCAS89 benchmark circuits are provided. The results illustrate that with marginal increase in area overhead, if compared to ones with single s-a fault coverage, the proposed scheme also provides coverage for resistive bridging faults and high value of n for n-detect coverage. The results have also been verified in silicon using FPGAs