Test generation for delay faults in non-scan and partial scan sequential circuits

Abstract

We address the problem of generating tests for delay faults in non-scan and partial scan synchronous sequential circuits. A recently proposed transition fault model for sequential circuits (I) is considered. In this fault model. a transition fault is characterized by the fault site, the fault type and the fault size. The fault type is either slow-to-rise or slow-to-fall. The fault size is specified in units of clock cycles. It was observed that neither a comprehensive functional verification sequence nor a sequence with a high stuck-at fault coverage gives a high transition fault coverage for sequential circuits. Deterministic test generation for delay faults is required to raise the coverage to a reasonable level. In this papex, we present a test generation algorithm for this fault model. With the use of a novel fault injection technique, tests for transition faults can be generated by using a stuck-at fault test generation algorithm with some modifications. The new test gen- erator DATEST (Delay fault Automatic TEST generator for sequential circuits) has been integrated with our sequential circuit delay fault simulator, TFSIM. Experimental results for ISCAS-89 benchmark circuits and some AT&T designs are presented. For partial scan circuits, we first describe a test application scheme for detecting transition faults. Modifications on test gen- eration and fault simulation algorithms required for partial scan circuits are presented. Experimental results on large benchmark circuits show that a high transition fault coverage can be achieved for the partial scan circuits designed using the cycle-breaking POI. faults, not mentioning for delay faults. Therefore, we believe that deterministic delay test generation is required even if a set of com- prehensive functional verification vectors is available. In this paper, we address the problem of generating tests for delay faults in non-scan or partial scan sequential circuits. We assume that the sequential circuit under test is synchronous. Mul- tiple clocks and multiple phases are allowed. The entire input sequence is applied at a rated speed. At the end of each vector and clock application. the primary outputs are observed. There- fore, the outputs are also observed at a fixed rate. Under this test application scheme, which is a typical scheme used for applying functional vectors, fault sizes of delay defects must be considered. Different excess delays caused by a fault will result in completely different logic behaviors. A recently proposed transition fault model for sequential circuits (I) that takes the fault size into account is used in this work. It is a generalization of the combina- tional circuit transition fault model (5). A brief description of the model will be given in the next section. In this work, we consider only non-robust tests for three reasons: (1) Fault simulation and test generation methods for non-robust gate delay faults can be made fully compatible with existing stuck-fault testing methods. With a novel fault injection technique, we transform the fault simulatiodtest generation process for non-robust delay faults into a fault simulationhest generation process for stuck-at faults. (2) The computational complexity is lower such that very large cir- cuits can be handled. (3) For many sequential circuits, a large number of faults is not robustly testable under the normal test application scheme. Therefore, the robust delay fault coverage may be very low and too pessimistic.