Abstract

In VLSI industry, image signal processing algorithms are developed and evaluated using software models before implementation of RTL and firmware. After the finalization of the algorithm, software models are used as a golden reference model for the image signal processor (ISP) RTL and firmware development. In this paper, we are describing the unified and modular modeling framework of image signal processing algorithms used for different applications such as ISP algorithms development, reference for hardware (HW) implementation, reference for firmware (FW) implementation, and bit-true certification. The universal verification methodology- (UVM-) based functional verification framework of image signal processors using software reference models is described. Further, IP-XACT based tools for automatic generation of functional verification environment files and model map files are described. The proposed framework is developed both with host interface and with core using virtual register interface (VRI) approach. This modeling and functional verification framework is used in real-time image signal processing applications including cellphone, smart cameras, and image compression. The main motivation behind this work is to propose the best efficient, reusable, and automated framework for modeling and verification of image signal processor (ISP) designs. The proposed framework shows better results and significant improvement is observed in product verification time, verification cost, and quality of the designs.

Highlights

  • Image signal processor (ISP) mainly corrects the output images of the sensor so that the best possible defects and noise-free images can be generated

  • It presents the image signal processor (ISP) development flow that we have developed going through algorithm investigation, algorithm development, ISP RTL implementation, and its functional verification using universal verification methodology- (UVM-)based verification environment

  • IP-XACT Flow In universal verification methodology (UVM)-based verification framework of image signal processor, register definition file for UVM REG register model, top-level address map file, register and data sequences file, data checker file to compare the output of ISP RTL with output of Python reference model, and functional coverage file are ISP IP/SoC specific

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Summary

Introduction

Image signal processor (ISP) mainly corrects the output images of the sensor so that the best possible defects and noise-free images can be generated. Universal verification methodology (UVM) is a generic methodology for the functional verification of hardware designs, mainly using simulation. Python reference models are used in universal verification methodology based verification framework of ISP RTL for its bit-true verification. This proposed framework shows better results and significant improvement is observed in product verification time (∼ 50% improvement), verification cost (∼20% reduction), and quality of the designs (∼75–80% improvement).

Related Work
ISP Development Flow
Functional Verification
Early Development of Verification Framework
IP-XACT Flow
Results and Discussion
Conclusion
Full Text
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