Abstract
The threshold voltage hysteresis in SiC power MOSFETs is rarely studied. This paper investigates the captureand emission-time constants of positive and negative charge trapped in the gate oxide and at the interface as a function of gate bias. We present a measurement technique which enables time-resolved measurement of the real ${V} _{\text {th}}$ during application-relevant bipolar ac high temperature gate stress. In addition, we use capture and emission time maps to explain the temperature dependence of $\Delta {\text V}_{\text {th}}$ after stress and are able to simulate $\Delta {\text V}_{\text {th}}$ after positive ac stress considering the full stress-history. Furthermore, we will show that the threshold voltage hysteresis has no harmful impact on switching operation in real applications.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callMore From: IEEE Transactions on Device and Materials Reliability
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
