Abstract
Modeling of the threshold voltage instabilities in SiC power MOSFETs is difficult due to the fast recovery of ΔV th after positive and negative gate bias stress. This work investigates the capture- and emission-time constants of positive and negative charge trapped in the gate oxide and at the interface as a function of gate bias and temperature. We present a measurement technique which enables time-resolved measurements of the real Vth during application-relevant bipolar AC high temperature gate stress (HTGS). We use capture and emission time (CET) maps to model the temperature and voltage dependence of the ΔV th after positive as well as negative gate stress. In addition, we provide a complete modeling approach for the ΔV th after long-term AC stress considering the full stress-history. Furthermore, we present a very accurate model for the short-term hysteresis during a bipolar AC period and we show that the threshold voltage hysteresis has no harmful effect on switching operation in real applications.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
