Abstract
Coarse Grained Reconfigurable Arrays (CGRAs) can exploit parallelism of compute-intense applications by distributing their workload across a set of Processing Elements (PEs). They are highly efficient in computation and flexible due to their reconfigurability. While these attributes make CGRAs highly interesting as general purpose hardware accelerators, their incorporation into a complete computing system raises severe challenges at the hardware and software level. To overcome the stage of a simulated concept, CGRAs need to be applied to the real-world in order to demonstrate the practicability of the overall system. This paper presents the integration of a CGRA into a control engineering environment targeting a Xilinx Zynq System on Chip (SoC). It focuses on the fully automated tool-chain mapping abstract engineering models to CGRA configurations, and on the SoC-internal runtime communication on hardware level.
Published Version
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