Abstract

Coarse Grained Reconfigurable Arrays (CGRA) are more area and energyefficient compared to FPGAs, if we consider applications that aredominated by arithmetical operations. Enabling the user to employCGRAs requires tools to create suitable CGRA instances and to programthem on a high abstraction level. In this contribution we brieflyexplain a CGRA archticture generator and we focus on the schedulerthat programs the generated CGRAs. This scheduler is able to work oninhomogeneous (concerning the operations in the processing elements) and irregular (concerning the connections between processing elements) compositions. Additionally, the scheduler is able to map complex controlflow onto the CGRA, which means nested loops, even containing controlflow in the loop body. This significantly increases the mappability ofapplication kernels.

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