Ultra-thin Flip-Chip Assembly for Heterogenous and Hybrid Integration

Abstract

Abstract Flip-chip packaging of thin-die, in fact any packaging of thin-die, is one of today’s most significant challenges for die handling. Despite the difficulties presented as the thickness of chips continues to decrease, the wide range of applications they have enabled across multiple industries has led to increasing interest, as evidenced by the growth in the cumulative total number of publications on thin silicon based electronics, including Ultra-Thin Chips (UTCs), thinning of Silicon-on-Insulator, and wafer thinning. Smart devices including labels, loggers, wearables, implantable medical, and IoT are in demand. A key area of difficulty in the packaging of thin chips comes from removing the individual chips from dicing tape due to the adhesive nature of the tape and die cracking and edge chipping characteristic of thin die. As the industry continues to embrace the benefits afforded by thin devices, two trends are being witnessed. Devices continue to grow larger in area and thinner in thickness. American Semiconductor’s automated production process for packaging and assembly of chips ≤35um in thickness will be presented. This includes details regarding needleless die eject, pick tip design for ultra-thin devices, ultra-thin flip-chip interconnects, thin-chip overcoat, process controls, and assembly on flexible circuit boards (FCB).