Abstract
The computing efficiency of modern column compression multipliers offers a highly efficient solution to the binary multiplication problem and is well suited for VLSI implementations. The various analyses are established more on compressors circuits particularly with Multiplexer (MUX) design. Conventionally, compressors are anatomized into XOR gate and MUX design. In this study, fully MUX based compressors, utilizing the CMOS transmission gate logic have been proposed to optimize the overall Power-Delay-Product (PDP). The proposed compressors are also used in the design and comparative analysis of 4×4-bit and 8×8-bit Wallace and Dadda multipliers operating in sub-threshold regime. The multipliers based on the proposed compressor designs have been simulated using 45 nm CMOS technology at various supply voltages, ranging from 0.3 to 0.5 V. The result shows on an average 89% improvement in the PDP of the proposed compressor blocks, when compared with the existing published results in sub-threshold regime. The multipliers designed using the proposed compressor blocks also show improved results.
Highlights
In order to maintain the rapid increase of high performance fidelity applications, emphasis will be on incorporation of low power energy efficient modules in future system design
The Wallace and Dadda Multipliers consist of three fundamental parts: A partial product reduction module to reduce the partial products matrix to an addition of only two operands, compressors to perform the partial product addition and a final adder part for the final computation of the binary result (Wallace, 1964; Dadda, 1965; Jayaraju et al, 2011)
These results show that proposed modules function properly at supply voltage as low as 0.3 V
Summary
In order to maintain the rapid increase of high performance fidelity applications, emphasis will be on incorporation of low power energy efficient modules in future system design. High input compressors are anatomized into XOR gates and carry generators are normally implemented by MUXs. different designs can be classified based on the critical path delay, in terms of the number of primitive gates. A 4-2 compressor cell can be implemented in many different logic structures In general, it comprises of three main modules, the first module is required to generate XOR/XNOR function, the second module is used to generate sum and the last module is used to produce the carry output.
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