Design of power efficient multiplexer using dual-gate FinFET technology

Abstract

This paper presents the design and analysis of a 2∶1 multiplexer. The conventional circuit of 2∶1 multiplexer(MUX) is used for the calculation of different parameters like power consumption, noise, delay, leakage power, etc. The multiplexer designed in this paper is suitable for low-power applications and works on very low supply voltage. Multiplexer is a digital circuit, it consists of 2N input and has n select line which are used to select the input line to transmit to the output. The multiplexer are used to expand the measure of information that can be sent over the system of a sure measure of time and bandwidth. Multiplexer comprises of multiple input signals and gives a single output switch. In this paper, a novel FinFET technique is used for the reduction of leakage power. The parameters of the conventional circuit and FinFET are compared and the performance of the multiplexer circuit is increased. The proposed multiplexer works on supply voltage of 0.7V. The design and simulation of FinFET based 2∶1 multiplexer is done by using 45nm technology at cadence virtuoso version 6.1 platform.