Ultra-Low Overhead Dynamic Watermarking on Scan Design for Hard IP Protection

Abstract

Unlike conventional legal means, digital watermark enables an effective self-protection mechanism for Very Large Scale Integration (VLSI) designers to protect their intellectual property (IP). However, existing watermarking techniques come with unpredictable and often high design and performance overhead, which makes them impractical. In this paper, we propose an ultra-low overhead watermarking scheme to protect hard IPs, the dominating form of commercial IPs. Our approach is based on the observation that an optimized scan design uses two complementary connections between two adjacent scan cells. Such scan design flexibility in the selection of local connection styles provides a vehicle to embed watermarking constraints. It can conveniently be implemented by local rewiring and/or introducing dummy scan cells. The test vectors will be changed accordingly to reflect the watermarked connection styles in order to guarantee the test coverage. This approach offers two unique features: 1) ultra-low overhead and 2) easy detectability. First, because the scan chain order is maintained and these changes are local, the proposed watermarking technique will introduce ultra-low overhead in terms of area, power, and speed. Next, watermark can be extracted from the test vectors and/or the corresponding scan output. Experimental results validate that the performance overhead is negligible (almost zero on the most cases) and the watermark is resilient to various possible attacks.