Two-dimensional model of symmetrical double-gate strained Si single Halo metal-oxide semiconductor field effect transistor with gate stack dielectric

Abstract

In this paper, a novel symmetrical double-gate strained Si single halo metal-oxide semiconductor field effect transistor with gate stack dielectric is proposed. The two-dimensional Poisson's equation is solved under suitable boundary condition by applying the parabolic potential approximation. This analytical model for the surface potential and the threshold voltage is derived. The strained Si channel is divided into two different doping regions, and the surface potential along the channel, compared with the normal double-gate device (uniform doping channel), exhibits a stepped potential variation, which can increase carrier transport speed. The influence of drain-source voltage on short channel effects (SCEs) is discussed. it is shown that threshold voltage decreases with Ge mole fraction increasing in butter layer, increases with the increase of the high-k layer dielectric permittivity of gate stack, and increases with the increase of doping concentration in the channel near the source, of which the physical mechanisms are analyzed and explained. Results show that the novel device can suppress threshold voltage drift and SCEs, which provides the basic guidance for designing the CMOS-based devices in nanometer scale.