Two‐dimensional Placement Using Tabu Search

Abstract

Search based placement of modules is an important problem in VLSI design. It is always desired that the search should converge quickly to a high quality solution. This paper presents a tabu search based optimization technique to place modules on a regular two‐dimensional array. The goal of the technique is to speed up the placement process. The technique is based on a two‐step placement strategy. The first step is targeted toward improving circuit routability and the second step addresses circuit performance. The technique is demonstrated through placement of several benchmark circuits on academic as well as commercial FPGAs. Results are compared to placements generated by commercial CAE tools and published simulated annealing based techniques. The tabu search technique compares favorably to published simulated annealing based techniques, and it demonstrates an average execution time speedup of 20 with no impact on quality of results when compared to commercial tools.