Truly Random Number Generator Based on a Ring Oscillator Utilizing Last Passage Time

Abstract

This brief covers the design and fabrication of a ring oscillator-based truly random number generator (TRNG), which was fabricated in 0.13- $\mu\hbox{m}$ CMOS technology. The randomness originates from the phase noise in a ring oscillator. Timing jitter resulting from crossing the threshold multiple times, i.e., last passage time (LPT), is exploited. Previously, the jitter model was developed and applied to the core delay cell of the slow VCO, part of the ring oscillator, where a slow slew rate phase was introduced to greatly increase phase noise. In this brief, the successful design of the entire TRNG was performed. This includes designing the circuit to avoid introducing correlation in the TRNG. Toward this end, novel timing circuitry is designed to properly control both the beginning and termination of this slow slew rate phase by tapping into the previous stage's output. 1/f noise also has to be minimized. Furthermore, the entire TRNG is now designed/implemented and fabricated, and experimental results are shown. The fabricated ring oscillator was shown to possess a timing jitter of 1.5 ns. Simulation under PVT variations of the entire cell shows that jitter variations are within 30%, showing that the designed control circuit was able to perform under such PVT variations. Entropy simulation with power supply variations applied to the TRNG was also run to assess its effectiveness as the biasing condition is changing. The randomness of the entire TRNG was assessed by applying the National Institute of Standards and Technology (NIST) tests. On those tests recommended by NIST to have longer bit streams, additional test measurements were performed on bit streams with increased length. Entropy tests for 20 k, 200 k, and 400 k measured bits were performed, resulting in entropy values all close to 1.