Trap studies in silicon nanowire junctionless transistors using low-frequency noise

Abstract

A method to envisage trap density in the semiconductor bandgap near the semiconductor/oxide interface of nanoscale silicon junctionless transistors (JLTs) is presented. JLTs are fabricated in a bottom-up fabrication technique using in situ highly doped nanowires grown by low pressure chemical vapor deposition. Low-frequency noise characterization of JLTs biased in saturation is conducted at different gate biases. The noise spectrum indicates either a Lorentzian or 1/f noise depending on the gate bias. Analysis of the results indicates very low trap densities in the order of 1016 cm−3eV−1. Low trap densities in these devices are associated with their simple fabrication technique, in situ oxide formation, and the absence of semiconductor junction and the ion implantation step in the process. A simple analysis of the low-frequency noise data leads to the density of the traps and their energy within the semiconductor bandgap and their location from the Si/SiO2 interface.