Towards low area overhead ARQ based soft error tolerant data paths for SRAM-based Altera FPGAs

Abstract

The SRAM-based FPGA, due to their high performance, has become a popular choice in today's electronic systems and are used in large number of applications. But in radiation harsh environment these FPGAs require some additional mechanism to cope up with soft errors. Modern FPGAs are built in 28nm technologies, where even combinational circuits are substantially vulnerable to soft errors. Such designs require soft error mitigation circuits in their data paths. Conventional soft error mitigation techniques such as triple modular redundancy are robust but their area overhead is three times as compared to normal design. In this paper a variant of automatic repeat request (ARQ) protocol is proposed, along with delayed redundancy to reduce area overhead. Synthesis results show an improvement of 9.1 and 10% in latency for Cyclone II and Stratix II FPGAs, respectively, with a 1.94 times improvement in resource utilization. Our synthesis results show that our implementation is not only better in terms of area overhead but if a soft error occurs once in 10 clock cycles the overall system throughput is better for the proposed architecture compared to TMR. To our knowledge this is the first work to implement ARQ based protocol utilizing delayed redundancy to mitigate soft errors in SRAM-based FPGAs.