Soft error aware pipelined architecture: Leveraging automatic repeat request protocol

Abstract

Reliability is a crucial factor in modern processors, which are designed in deep sub-micron (DSM) technologies and perform numerous tasks at high speed in less time. Modern DSM technologies are even more vulnerable to soft errors, which can propagate in pipeline processors and may lead to malfunctioning. Contemporary soft error mitigation techniques introduce redundancy in intermediate registers alone [6], [8], which addresses soft error occurrence in hardware registers only. However, in modern DSM technologies soft error can equally affect combinational circuits in the data path[1], hence in pipeline processors data paths also requires soft error mitigation. In this paper we propose a soft error mitigation technique in pipelined processors that addresses soft error in data paths. We utilized temporal redundancy in data path along with automatic repeat request (ARQ) protocol in all pipeline stages. Our novel ARQ based technique detects soft errors in the data path to process the reliable data to the successive stages of the pipeline. Our synthesis results show that our implementation is 50% better in terms of latency and requires 1.53 times lesser area overhead compared to contemporary state-of-art techniques [6], [7], [8].