Towards dynamic cache block placement for multi-processor NUCA

Abstract

The spectacular increasing speed of microprocessors is been handicapped by the modest evolution of memories speed. Thus, the pressure is put on the cache and in particular on the LLC (Low Level Cache) attempting to avoid costly access to main memory. Moreover, increasing both LLC size and number of cores per chip created an other problem : the non-uniformity of cache access. Indeed, LLC banks and processors are non-uniformly distant, penalizing hence cores attempting to access distant banks. We aim to improve NUCA (Non Uniform Cache Access) blocks migration. The new NUCA controller monitors block accesses according to each one's behavior. In this paper we present the first step of our approach where we attempt to observe blocks behavior in order to categorize them in the goal to treat differently each category.