Toward low-power-consumption source-gated phototransistor

Abstract

The power consumption is challenging the next-generation electronic and optoelectronic devices. In this Letter, the n-type source-gated transistor (SGT) enabled by CdS nanobelt is investigated in detail, demonstrating the expected low power consumption, along with impressive photodetection performance. The SGT is realized by deliberately introducing the Schottky barrier at the source of the staggered-electrode transistor, exhibiting a small saturated voltage (VSAT) of 0.84 ± 0.21 V and a remarkably low power consumption of 7.56 ± 4.01 nW. Under illumination, the as-constructed SGT also shows a low power consumption of 7.58 nW, which is much lower than that of the most reported phototransistors operating in the saturated region. Moreover, the source-gated phototransistor also shows a high responsivity of 2.54 × 103 A W−1 and a high detectivity of 6.72 × 1012 Jones. All results imply that the as-constructed low-power-consumption source-gated phototransistor promises next-generation high-performance electronic and optoelectronic devices.