Abstract
Spintronic domain-wall memories (DWMs) offer improved memory density and energy compared to conventional memories but are susceptible to shifting faults. We propose PIETT (<b>P</b>inning, <b>I</b>nsertion, <b>E</b>rasure, and <b>T</b>ranslation-fault <b>T</b>olerance) for improved misalignment correction versus the state of the art. PIETT proposes a derived error correction combined with multi-domain access approach to detect and correct a minimum of three misalignment faults after an arbitrary shift distance. Moreover, we characterize the rate of both misalignment and pinning faults in DWM nanowires and demonstrate that pinning faults are a significant concern to DWM. As such, PIETT is the first method combine correction of misalignment and pinning faults in random access DWMs. It also introduces novel PIETT Transverse Access Points (TAPs) that utilize a novel write access mode which can set/reset multiple domains in a single intrinsic operation and can store shift distance detection codes. By allowing checks between shifts of the intrinsic shift distance (<i>e.g.,</i> 3 domains), using a single TAP per nanowire expands misalignment protection and determines the needed corrective shifts to correct faults in all nanowires. Two TAPs expands misalignment protection to correct misalignment by more than one position and detects pinning by detecting different shift distances at each extremity of the nanowire. PIETT leverages knowledge of pinned nanowire locations to guide a modified SECDED ECC with one additional parity bit stored in additional parity nanowires. Thus, PIETT in TAP mode can correct unlimited, potentially multi-position, misalignment faults and either up to three pinning faults or up to two pinning faults with up to one bit-flip fault using scrubbing. PIETT provides eight to 21 orders of magnitude improvement in mean-time-to-failure with similar or better area overhead and only a 1% system performance degradation compared to state of the art DWM misalignment correction.
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