Spintronic Memories: From Memory to Computing-in-Memory

Abstract

Spintronic memory has been considered as one of the most promising nonvolatile memory candidates to address the leakage power consumption in the post-Moore’s era. To date, the spintronic magnetic random access memory (MRAM) family has mainly evolved in four-generation technology advancement, from toggle-MRAM (product in 2006), to STT-MRAM (product in 2012), to SOT-MRAM (intensive R&D today), and to VCMA- MRAM (intensive R&D today). In addition, another spintronic memory, named racetrack memory (RM), proposed in 2008, has also evolved in two generations from domain wall (DW) based RM to skyrmion-based RM. On the other hand, from the architectural perspective, data transfer bandwidth and the related power consumption has become the most critical bottleneck in vonNeumann computing architecture, owing to the separation of the processor and the memory units and the performance mismatch between the two. Realization of the unity of computing and memory in the same place has opened up a promising research direction of computing-in-memory (CIM). Spintronic memory could be a promising technology to implement the CIM paradigm, owing to its intrinsic processing capability. Lots of interests have been attracted and a number of attempts have been made in this field, within both MRAM and RM. In this paper, we perform a mini review on the R&D evolution of spintronic memories: from memory to computing-in-memory. Particularly, we will introduce our recent work on advanced spintronic memories as well as CIM paradigms implemented within spintronic memories.