Abstract
Total ionizing dose (TID) effects are investigated in a nanosheet gate-all-around field effect transistor using three-dimensional technology computer aided design simulation. TID is a reliability concern in terms of building up trap charges in any dielectric surrounding the transistor body. In this work, the impact of trap charges on different dielectrics including gate oxide, gate spacer and shallow trench isolation is discussed. The TID vulnerabilities for various channel characteristics are compared. Methods for suppressing the manifestation of trap charges are suggested.
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