Time‐to‐digital convertor based on resolution control

Abstract

In this paper, a coarse-fine time-to-digital converter (TDC) based on Vernier delay line (VDL) was proposed. A new digital circuit was developed for tree delay line and this method led to high resolution and low power consumption. The TDC core was based on the pseudo-differential digital architecture that made it insensitive to nMOS and pMOS transistor mismatches. It also took advantage of a VDL used in conjunction with an asynchronous read-out circuitry. The time interval resolution was equal to the difference of delay between buffer of upper and lower chains. Then, with added extra chain in lower delay line, resolution can be controlled and area and power consumption was reduced. Measurement results of the TDC showed the resolution of 4.5 ps and output dynamic range of 32-bit and the differential non-linearity was always less the one least significant bits (1LSB), while the integral non-linearity showed the maximum of one least significant bits. This TDC achieved the consumption of 248.9 µW from 1.2 V supply.