A low power high resolution time to digital converter for ADPLL application

Abstract

A new nonlinear Time to Digital Converter (TDC) based on time difference amplification is the proposed. A new gain compensation method is presented to expand the DR of conventional ×2 Time Amplifiers (TAs). Instead of conventional gain compensation approach based on changing strength of current sources, the proposed technique uses current difference which results more stable gain over wider DR. In order to avoid two different paths of the stages, a sign bit detection part is the proposed at the front of the TDC to allow using one path of stages for both positive and negative input time differences. As a result, the most advantages of the proposed TDC are its high resolution, wide DR, and low power consumption. The postlayout simulations of the proposed TDC are done by Cadence Spectre using TSMC 0.18um COMS technology. DR of the ×2 TA is expanded to 200ps only with 6% gain error. Resolution and DR of the TDC are 0.7ps and 630ps, respectively. Power consumption at 50Msps throughput and 1.2V supply voltage is 520uW.