Time-Predictable Computer Architecture

Martin Schoeberl

doi:10.1155/2009/758480

Abstract

Today's general-purpose processors are optimized for maximum throughput. Real-time systems need a processor with both a reasonable and a known worst-case execution time (WCET). Features such as pipelines with instruction dependencies, caches, branch prediction, and out-of-order execution complicate WCET analysis and lead to very conservative estimates. In this paper, we evaluate the issues of current architectures with respect to WCET analysis. Then, we propose solutions for a time-predictable computer architecture. The proposed architecture is evaluated with implementation of some features in a Java processor. The resulting processor is a good target for WCET analysis and still performs well in the average case.

Highlights

Standard computer architecture is driven by the following paradigm: Make the common case fast and the uncommon case correct [1]
This design approach leads to architectures where the worst-case execution time (WCET) is high and hard to predict by static analysis
We evaluate some of the proposed timepredictable architectural features with JOP [2], an implementation of a Java processor

Summary

Introduction

Standard computer architecture is driven by the following paradigm: Make the common case fast and the uncommon case correct [1]. This design approach leads to architectures where the worst-case execution time (WCET) is high and hard to predict by static analysis. Classic enhancements in computer architectures are pipelining, instruction and data caching, dynamic branch prediction, out-of-order execution, speculative execution, and fine-grained chip multithreading. These features are increasingly harder to model for the low-level WCET analysis.

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