Threshold voltage in short channel polycrystalline silicon thin film transistors: Influence of drain induced barrier lowering and floating body effects

Abstract

The threshold voltage (VT) variations induced by the drain bias (Vds) are investigated in polycrystalline silicon thin film transistors (TFTs), with channel length ranging from 20 to 0.4 μm, by combining experimental measurements and two-dimensional (2D) numerical simulations. A careful analysis of the electrical characteristics in both subthreshold and off regime is performed, by taking in account also the effects of the leakage current field enhanced mechanisms on the overall generation-recombination rate. We show that the main causes of VT variations are the drain induced barrier lowering (DIBL) and floating body effects (FBEs), induced by impact ionization. The relative influence of FBEs and DIBL is analyzed by performing numerical simulations with or without including the impact ionization model. A detailed analysis of the 2D Poisson equation has allowed to identify and evaluate the contributions of DIBL and FBEs to the threshold voltage variation when both are present. It is found that, in short channel TFTs at high drain bias, the VT variations can’t be attributed to DIBL effect alone and there is a noticeable contribution of the FBEs to the threshold voltage reduction. From the numerical simulations, the influence of FBEs and DIBL on the electrostatic barrier at source junction and its reduction for increasing Vds is analyzed for long and short channel TFTs.