Three-Dimensional Mechanistic Modeling of Gate Leakage Current in High- κ MOSFETs

Abstract

Gate leakage current is an issue for the reliability of modern high-$\ensuremath{\kappa}$ MOSFETs. Although various physical models describing both direct tunneling and trap-assisted contribution of leakage current have been presented in the literature, many of them treats traps in the dielectric as a continuum distribution in energy and position, and trap-to-trap transport of electrons has so far been mostly neglected or not treated three dimensionally. In this work, we present a mechanistic model for calculation of gate leakage current in high-$\ensuremath{\kappa}$ MOSFET multilayer stacks based on multiphonon trap-assisted tunneling theory, taking into account the intrinsic three-dimensional (3D) discreteness of traps in the dielectric. Our model can to a good approximation reproduce the experimental results at different dielectric thicknesses, gate voltages, temperatures, and different gate materials. We find that in realistic devices, the 3D trap-to-trap transport of electrons contributes a non-negligible part to the gate leakage current. This contribution is more pronounced at low-voltage device operations, which is important for low-power applications. We calculate the intrinsic fluctuation of gate leakage current due to positional and energetic disorder of traps in the dielectric, and conclude that positional disorder is more important than energetic disorder for realistic material parameters. The calculated gate leakage current depends sensitively on temperature, trap energy, and trap density. We provide a computationally efficient 3D master equation approach that enables 3D mechanistic simulation of ${10}^{3}$ traps on the order of minutes on a standard desktop computer.