Investigation of gate oxide traps effect on NAND flash memory by TCAD simulation**Project supported by the SanDisk Info Tech Shanghai, China and the Institute of Microelectronic Materials & Technology, School of Materials Science and Engineering, Shanghai Jiao Tong University, China.

Abstract

The effects of gate oxide traps on gate leakage current and device performance of metal–oxide–nitride–oxide–silicon (MONOS)-structured NAND flash memory are investigated through Sentaurus TCAD. The trap-assisted tunneling (TAT) model is implemented to simulate the leakage current of MONOS-structured memory cell. In this study, trap position, trap density, and trap energy are systematically analyzed for ascertaining their influences on gate leakage current, program/erase speed, and data retention properties. The results show that the traps in blocking layer significantly enhance the gate leakage current and also facilitates the cell program/erase. Trap density ∼ 1018 cm−3 and trap energy ∼ 1 eV in blocking layer can considerably improve cell program/erase speed without deteriorating data retention. The result conduces to understanding the role of gate oxide traps in cell degradation of MONOS-structured NAND flash memory.