Threading Dislocation Reduction of Ge by Introducing a SiGe/Ge Superlattice

Abstract

Ge growth on Si is essential e.g. for photonics device integration (e.g. Ge photodiode) into Si based CMOS platform (1). However, due to 4.2% of lattice mismatch between Ge and Si, misfit dislocations (MD) and threading dislocations (TD) are introduced for strain relaxation after exceeding critical thickness. In order to realize low-darkcurrent Ge photodiode, improvement of crystallinity is important. High quality Ge growth techniques by combining various annealing techniques (at 800~850oC) are reported (2-3). However, because of low melting point of Ge (937oC), the Ge growth process is typically integrated at the last part of front-end process. Therefore, these annealing processes are affecting device parameters of existing devices. In previous paper, we reported Ge/SiGe superlattice (SL) fabrication and found improvement of TD density (TDD) by increasing Si composition of SiGe in the SL (4). Here we report TDD improvement of Ge by introducing the SL without annealing.Ge growth with SiGe/Ge SL is carried out using reduced pressure chemical vapor deposition system. Si(100) wafers are used. After an HF last cleaning, the wafer is loaded into reactor and baked at 1000oC and cooled down to 600oC in H2 and further cooled down to 350oC in N2. After that 100 nm-thick seed Ge is deposited using N2-GeH4 gas. Then the wafer is heated up to 500oC in H2 and Ge/SiGe superlattice is fabricated using H2-GeH4 and H2-SiH4-GeH4 gases, respectively. Furthermore, 2.8 µm thick Ge is deposited at 550oC using H2-GeH4 gas.Thickness is measured by cross section SEM and spectroscopic ellipsometry. TDD is determined by Secco defect etching technique. Strain and relaxation of Ge and SiGe layers are measured by XRD reciprocal space mapping. Distribution of the MD and the TD are measured by cross section TEM.In the case of direct Ge growth on Si (Fig. 1a), MDs are formed at interface between Ge and Si. TDs are spreading into the Ge layer. Some of the TDs are long and extending to surface. These MD and TD formations are due to the lattice mismatch between Ge and Si. On the other hand, in the case of Ge sample grown on ×20 Si0.3Ge0.7 / Ge SL (Fig. 1b), most of MDs are formed at interface between 100 nm-thick Ge buffer and Si substrate. Additionally high density of TDs are observed in the Ge buffer and the SL layer. In the SL layer, lower TDD is observed in the upper part compared to that in the deeper part. At the interface between upper 2.8 µm thick Ge and the SL layer, MD and high density of TDs toward lateral direction is observed indicating relaxation. TDD in the 2.8 µm thick Ge layer seems to be lower compared to that in Fig. 1a).In the case of direct Ge growth on Si, TDD of ~7.5×108 cm-2 is obtained (Fig. 2). The TDD is comparable to previously reported results (2). By depositing 2.8 µm thick Ge on Si0.2Ge0.8 SL, TDD is decreased to ~5.4×108 cm-2. With decreasing Ge concentration of SiGe layer of the SL, decrease of TDD is observed until 40%. However, by replacing SiGe layers to mono-layers of Si, increased TDD is observed, which might be due to too high strain at interface between Si and SiGe.Figure 3 shows TDD of 2.8 µm thick Ge deposited on Si0.2Ge0.8/Ge SL with different Si0.2Ge0.8 and Ge thickness combination without changing periodicity of the SL. Lower TDD is observed when the 2.8 µm thick Ge is deposited on the SL with higher Si0.2Ge0.8 thickness. Possible reason is higher degree of relaxation of the SL layer.In Fig. 4, TDD of 2.8 µm thick Ge deposited on SLs of various lattice parameters are shown. By reducing lateral lattice parameter of the SiGe/Ge SL by increasing SiGe thickness or Si concentration, TDD decreases. The reduction of the TDD is fitting to one line for both cases. These results indicate that higher plastic relaxation of the SL occurs on the Ge buffer due to increased compressive strain of SiGe in the SL, and the TDD reduction of the Ge on the SL may be caused by similar mechanism of reverse graded buffer. By introducing SiGe/Ge SL, multiple effect of the reverse graded buffer may be expected. Reference (1) S. Lischke et al. Proc. IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM) , (2014) 29(2) Y. Yamamoto et al Solid-State Electron. 60 (2011) 2(3) Y. Yamamoto et al. Semicond. Sci. Technol. 33 (2018) 124007(4) Y. Yamamoto et al. Jpn. J. Appl. Phys. 59, SGGK10 (2020) Figure 1