Thread-criticality aware dynamic cache reconfiguration in multi-core system

Abstract

To alleviate high energy dissipation of cache memory, some research has proposed to reconfigure cache parameters such as cache capacity, number of way associative, and cache line size during program phase changes. However, none of previous research on cache reconfiguration takes thread criticality into consideration. In this paper, we dynamically predict thread criticality of a parallel application and tune our cache memory architecture accordingly. The experimental results show that our method not only reduces 42% energy consumption, but also improves the system performance by 4% compared to the baseline cache setting without reconfiguration. Compared with the work by Chen et al. [1] where cache capacity is configured based on its hit count, our method yields extra 16% energy reduction and 7% performance improvement. Compared with the work by Gordon-Ross et al. [2] where cache always select the configuration with the minimum energy consumption for the current interval, our result has 8% more energy reduction and 12% more performance improvement.