Leakage energy reduction in cache memory by data compression

Abstract

Cache memory is effective in bridging a growing speed gap between a processor and relatively slow external main memory. Almost all of today's commercial processors, not only high-performance microprocessors but embedded ones, have on-chip cache memories. However, energy consumption in the cache memory would approach or exceed 50% of the total consumption by the processors, which leads to a serious problem in terms of allowable temperature and performance improvement. An important point to note is that, in the near future, static (leakage) energy will dominate the energy consumption in deep sub-micron processes. In this paper, we propose cache memory architecture that exploits gated-Vdd control per cache block and a dynamic data compression scheme in the secondary cache, and achieves efficient reduction of static energy consumed by the secondary cache memory. In the simulation using SPEC95 integer benchmarks, our technique reduced about 45% of leakage energy in the cache at maximum, and about 28% on average.