Thin-Film Transistors With Neodymium-Incorporated Indium–Zinc-Oxide Semiconductors

Abstract

A thin-film transistor (TFT) with a neodymium-doped indium–zinc-oxide (NIZO) channel layer was fabricated. It was found that the Nd element uniformly distributed in the whole NIZO films, which revealed a nanocrystalline structure, implying that Nd was incorporated into the IZO lattice rather than segregated as clusters. The NIZO TFT annealed at 300 °C showed a saturation mobility of 22.7 cm $^{2}\text{V}^{-1}\text{s}^{-1}$ , a turn-ON voltage of −1.32 V, a subthreshold swing (SS) of 0.23 V/decade, and small turn-ON voltage shift under negative gate bias stress (−0.42 V) and positive gate bias stress (0.40 V). As the annealing temperature increased, the threshold voltage of the NIZO TFTs became more and more negative. Compared with IZO TFTs without Nd, NIZO TFTs exhibited lower SS and less turn-ON voltage shift as the annealing temperature increased. It was found that the free carriers of NIZO can be lowered even with a small amount of Nd ( $\sim 1$ %). When annealed at a temperature of as high as 400 °C, the oxygen out-diffusion effect of NIZO was not as serious as that of IZO. Detailed studies showed that Nd atom could suppress the formation of oxygen vacancies due to the strong bonding strength of Nd–O (703 kJ/mol).