Thin-Film Strained-SOI CMOS Devices—Physical Mechanisms for Reduction of Carrier Mobility

Abstract

We have examined physical mechanisms responsible for the reduction in both electron and hole mobility in strained-silicon-on-insulator (SOI) CMOS devices with thin strained-Si layers. A slight decrease in the electron mobility with thinning strained-Si layers is attributable to the quantum-mechanical confinement effect of the inversion layer electrons, originating in the conduction band offset of the strained-Si layers. Also, the diffusion of Ge atoms into the SiO/sub 2//strained-Si interface is found to generate interface states near the valence band edge, leading to the reduction in hole mobility in the lower E/sub eff/ region through Coulomb scattering. Moreover, the decrease in hole mobility enhancement in both thin and thick strained-Si structures at the higher electric field is caused by the reduction of the energy splitting between the heavy and the light hole bands, with an increase in the electric field. Based on considerations of these factors affecting the mobility reduction, the strained-Si thickness and the Ge content have been designed to realize high-speed strained-SOI CMOS under the 90-nm technology and beyond.