Abstract
Due to large mismatch in coefficients of thermal expansion between the copper via and the silicon of Through Silicon Via(TSV), significant thermal stresses will be induced at the interfaces of copper/dielectric layer (usually SiO 2 ) and dielectric layer/silicon when TSV structure is subjected to subsequent temperature loadings, which would influence the reliability and the electrical performance of interconnects. As a solution, a modified through silicon via was proposed. The thin SiO2 dielectric layer is replaced by a thick polymer isolation layer. Conformal copper plating is used to realize the connection and the remaining hole in the copper via is filled with polymer material. In this work, thermo-mechanical finite element method (FEM) was used to simulate copper filled and polymer filled TSV structures in order to analyze the thermo-mechanical behavior subjected to a load of temperature cycling. Several configurations were studied, including diameter of the copper via and polymer filled via, the aspect ratio H/D, the thickness of parylene dielectric layer. Different selections of filling on the copper via such as polyimide, BCB, epoxy and underfill (FP4256) were compared with the calculation results. The modeling results show that thermal stresses and the risk of failure in the through silicon via can be significantly reduced by use of a soft dielectric layer and polymer filled material.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.