The electromigration failure mechanism for TSV process

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TSV (Through Silicon Via) is the key component in fabricating 3D ICs and device packaging which has the advantages of lower power consumption, higher integration density and shorter interconnection length. TSV is a composite structure fabricated by process filling electroplated copper into etched silicon via, it consists of Cu/Ta/TaN/SiO2/Si multiple interfaces with roughness formed in the via etching process. In the TSV structure, more difference in coefficient of thermal expansion between copper and silicon leads to high thermal stress and related reliability issues, but fewer TSV EM works have been reported. Thus, TSV test structure with M1 of aluminum and backside redistribution layer of copper was designed and tested to evaluate EM reliability performance. Generally, the void nucleation and growth induce resistance change, and then impact expected metal interconnection performance. In our study, an unfamiliar EM failure mechanism of TSV was observed. No typical void was found, but barrier damage and Cu diffusion were observed in test. From failure analysis result, it is considered that EM failure mechanism of TSV consists of several major stages, including (1) barrier damage, (2) Cu diffusion and (3) CuAl alloy form. With the CuAl alloy formed, resistance of metal interconnection increases, so it induces EM failure.